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FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843207-350
GENERAL DESCRIPTION
T h e I C S 8 4 3 2 0 7 - 3 5 0 i s a l ow p h a s e - n o i s e IC S frequency margining synthesizer that targets HiPerClockSTM clocking for high performance interfaces such as SPI4.2 and is a member of the HiPerClockSTM family of high performance clock solutions from IDT. In the default mode, each output can be configured individually to generate an 87.5MHz, 175MHZ or 350MHz LVPECL output clock signal from a 14MHz crystal input. There is also a frequency margining mode available where the device can be configured, using control pins, to vary the output frequency up or down from nominal by 5%. The ICS843207-350 is provided in a 48-pin LQFP package.
FEATURES
* Seven independently configurable LVPECL outputs at 87.5MHz, 175MHz or 350MHz * Individual high impedance control of each output * Selectable crystal oscillator interface designed for 14MHz, 18pF parallel resonant crystal or LVCMOS single-ended input * Output frequency can be varied 5% from nominal * VCO range: 620MHz - 750MHz * Full 3.3V supply mode * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 33 4 5 32 48-Pin LQFP 6 7mm x 7mm x 1.4mm 31 package body 30 7 Y Package 8 29 Top View 9 28 27 10 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
SEL2 SEL3 SEL4 SEL5 SEL6 SEL7 SEL8 SEL9 SEL10 SEL11 SEL12 SEL13
VCCO Q0 nQ0 Q1 nQ1 VEE VCCO Q2 nQ2 Q3 nQ3 VCCO
ICS843207-350
VCCA VCC VCCO nQ6 Q6 VEE VCCO nQ5 Q5 nQ4 Q4 VCCO
BLOCK DIAGRAM
00 HiZ
01 /2 10 /8 11 /4
Q0 nQ0
Pullup
2 SEL[1:0]
00 HiZ
01 /2 10 /8 11 /4
Pullup
Q1 nQ1
2
SEL[3:2] Q2 nQ2
IDT TM / ICSTM LVPECL FREQUENCY MARGINING SYNTHESIZER
REF_CLK VEE MR MARGIN MODE
SEL1 SEL0 nPLL_SEL VCC XTAL_IN XTAL_OUT nXTAL_SEL
00 HiZ
01 /2 10 /8 11 /4
Pullup
nPLL_SEL Pulldown
14MHz
2
SEL[5:4] Q3 nQ3
XTAL_IN
OSC
1 0 0
00 HiZ
01 /2 10 /8 11 /4
Pullup
XTAL_OUT REF_CLK Pulldown nXTAL_SEL Pulldown
0 1
2
Predivider /2
1
Phase Detector
SEL[7:6] Q4 nQ4
VCO
620 - 750MHz
0 00 HiZ
01 /2 10 /8 11 /4
/50
00 HiZ
01 /2 10 /8 11 /4
Pullup
2
SEL[9:8] Q5 nQ5
1
/95 /105
MODE Pulldown MARGIN Pulldown MR
Pulldown
Pullup
2
SEL[11:10] Q6 nQ6
To O/P Dividers
00 HiZ
01 /2 10 /8 11 /4
Pullup
2
SEL[13:12]
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ICS843207-350 FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
FUNCTIONAL DESCRIPTION
The ICS843207-350 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A 14MHz fundamental crystal is used as the input to the on chip oscillator. The output of the oscillator is fed into the pre-divider. In frequency margining mode, the 14MHz crystal frequency is divided by 2 and a 7MHz reference frequency is applied to the phase detector. The VCO of the PLL operates over a range of 620MHz to 750MHz. The output of the M divider is also applied to the phase detector. The default mode for the ICS843207-350 is a nominal VCO frequency of 700MHz with each output configurable to divide by 2, 4 or 8. The nominal output frequency can be changed by placing the device into the margining mode using the mode pin and using the margin pin to change the M feedback divider. Frequency margining mode operation occurs when the MODE input is HIGH. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. The output of the VCO is scaled by an output divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle. The relationship between the crystal input frequency, the M divider, the VCO frequency and the output frequency is provided in Table 1A. When changing back from frequency margining mode to nominal mode, the device will return to the default nominal configuration described above.
TABLE 1A. FREQUENCY SELECT FUNCTION TABLE
XTAL (MHz) 14 14 14 14 SELx 0 0 1 1 SELx-1 0 1 0 1 VCO (MHz) 70 0 700 700 700 Output Divider N/A 2 8 4 Output Frequency (MHz) HiZ 350 87.5 175
TABLE 1B. FREQUENCY MARGIN FUNCTION TABLE
MODE 1 0 1 MARGIN 0 X 1 XTAL (MHz) 14 14 14 Pre-Divider (P) 2 1 2 Feedback Divider 95 50 105 VCO (MHz) 665 700 735 % Change -5.0 Nom. Mode +5.0
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TABLE 2. PIN DESCRIPTIONS
Number Number 1, 7, 12, 25, 30, 34 2, 3 4, 5 6, 16, 31 8, 9 10, 11 13 14 Name Name VCCO Q0, nQ0 Q1, nQ1 VEE Q2, nQ2 Q3, nQ3 MODE Margin Type Type Power Ouput Ouput Power Ouput Ouput Input Input Pulldown Pulldown Description Description Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. MODE pin. LOW = default mode. HIGH = frequency margining mode. See Table 4B. LVCMOS/LVTTL interface levels. Sets the frequency to 5% in frequency margining mode. See Table 1B. LVCMOS/LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go LOW and inver ted outputs nQx to go HIGH. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Reference input clock. LVCMOS/LVTTL interface levels. Cr ystal select pin. Selects between the cr ystal and the reference clock inputs. LVCMOS/LVTTL interface levels. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Core supply pins. PLL select pin. When HIGH, PLL is bypassed and input is fed directly to the output dividers. When LOW, PLL is enabled. LVCMOS/LVTTL interface levels.
15 17 18 19, 20 21, 35 22 23, 24, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48 26, 27 28, 29 32, 33 36
MR REF_CLK nXTAL_SEL XTAL_OUT, XTAL_IN VCC nPLL_SEL SEL0, SEL1, SEL2, SEL3, SEL4, SEL5, SEL6, SEL7, SEL8, SEL9, SEL10, SEL11, SEL12, SEL13 Q4, nQ4 Q5, nQ5 Q6, nQ6 VCCA
Input Input Input Input Power Input
Pulldown Pulldown Pulldown
Pulldown
Input
Pullup
Output divider select pins. See Table 1A. LVCMOS/LVTTL interface levels.
Ouput Ouput Ouput Power
Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Analog supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
TABLE 4A. nXTAL_SEL CONTROL INPUT FUNCTION TABLE
Input nXTAL_SEL 0 1 Selected Source XTAL_IN, XTAL_OUT REF_CLK
TABLE 4B. MODE CONTROL INPUT FUNCTION TABLE
Input MODE 0 1 Condition Q0:Q6, nQ0:nQ6 Default Mode Frequency Margining Mode
IDT TM / ICSTM LVPECL FREQUENCY MARGINING SYNTHESIZER
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VCC + 0.5V 50mA 100mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 65.7C/W (0 mps)
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VCCO = VEE = OV, TA = 0C TO 70C
Symbol Parameter VCC VCCA VCCO IEE ICCA Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VCC - 0.13 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 VCC 3.465 210 13 Units V V V mA mA
TABLE 5B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VEE = OV, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current REF_CLK, MARGIN, MODE, nPLL_SEL, MR, nXTAL_SEL SEL[0:13] REF_CLK, MARGIN, MODE, nPLL_SEL, MR, nXTAL_SEL SEL[0:13] t/v Input Transition Rise/Fall Rate SEL[0:13], MODE Test Conditions VCC = 3.3V VCC = 3.3V VCC = VIN = 3.465 VCC = VIN = 3.465 VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 20 Minimum Typical 2 -0.3 Maximum VCC + 0.3 0.8 150 5 Units V V A A A A ns/V
IIL
Input Low Current
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PRELIMINARY
TABLE 5C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VEE = OV, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. 12.4 Test Conditions Minimum Typical Maximum 14 15 40 7 300 Units MH z pF W Fundamental
TABLE 7. AC CHARACTERISTICS, VCC = VCCO = 3.3V5%, VEE = OV, TA = 0C TO 70C
Symbol fOUT fIN Parameter Output Frequency Input Frequency REF_CLK Mode = LOW 350MHz, (12kHz - 20MHz) Mode = LOW 175MHz, (12kHz - 20MHz) Mode = LOW 87.5MHz, (12kHz - 20MHz) 20% to 80% Output Divider = /2 Output Divider = 2 Test Conditions N = /2 N = /4 N = /8 Minimum 310 155 77.5 12.4 Typical 350 175 87.5 14 1.54 1.48 1.61 300 42 46 600 58 64 Maximum 375 187.5 93.75 15 Units MHz MHz MHz MHz ps ps ps ps % %
t jit(O)
RMS Phase Jitter, Random; NOTE 1
t R / tF odc
Output Rise/Fall Time Output Duty Cycle
NOTE 1: Characterized using a 14MHz cr ystal.
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PRELIMINARY
TYPICAL PHASE NOISE AT 175MHZ
10 Gigabit Ethernet Filter 175MHz
RMS Phase Noise Jitter 12kHz to 20MHz = 1.48ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
TYPICAL PHASE NOISE AT 350MHZ
10 Gigabit Ethernet Filter 350MHz
RMS Phase Noise Jitter 12kHz to 20MHz = 1.54ps (typical)
NOISE POWER dBc Hz
IDT TM / ICSTM LVPECL FREQUENCY MARGINING SYNTHESIZER
Phase Noise Result by adding 10 Gigabit Ethernet Filter to raw data OFFSET FREQUENCY (HZ) Raw Phase Noise Data Phase Noise Result by adding 10 Gigabit Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V 2V
Phase Noise Plot
VCC, VCCO
Qx
VCCA
Noise Power
SCOPE
Phase Noise Mask
LVPECL
nQx VEE
f1 Offset Frequency f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0:nQ6 80% Q0:Q6 80% VSW I N G
t
PERIOD
t PW
Clock Outputs
20% tR tF
20%
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843207-350 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VCCA pin.
3.3V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843207-350 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 14MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p
FIGURE 2. CRYSTAL INPUt INTERFACE
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PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output
VDD
impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
IDT TM / ICSTM LVPECL FREQUENCY MARGINING SYNTHESIZER
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PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843207-350. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843207-350 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 210mA = 727.65mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 7 * 30mW = 210mW
Total Power_MAX (3.63V, with all outputs switching) = 727.65mW + 210mW = 937.65mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming air flow at 1 meter per second and a multi-layer board, the appropriate value is 55.9C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.938W *55.9C/W = 122.4C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE JA FOR 48-PIN LQFP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 65.7C/W
1
55.9C/W
2.5
52.4C/W
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PRELIMINARY
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, V
OUT
=V
OH_MAX
=V
CCO_MAX
- 0.9V
(V
CCO_MAX
-V
OH_MAX
) = 0.9V
*
For logic low, VOUT = VOL_MAX = VCCO_MAX - 1.7V (VCCO_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/R ] * (VCCO_MAX - VOH_MAX) =
L L
[(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCCO_MAX - 2V))/R ] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/R ] * (VCCO_MAX - VOL_MAX) =
L L
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 9. JAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 65.7C/W
1
55.9C/W
2.5
52.4C/W
TRANSISTOR COUNT
The transistor count for ICS843207-350 is: 4380
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PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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PRELIMINARY
TABLE 11. ORDERING INFORMATION
Part/Order Number 843207CY-350 843207CY-350T 843207CY-350LF 843207CY-350LFT Marking 43207C350 43207C350 3207C350L 3207C350L Package 48 Lead LQFP 48 Lead LQFP 48 Lead "Lead-Free" LQFP 48 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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